Peripheral storage hierarchies have been used for years for providing an apparent store as suggested by Eden, et al in U.S. Pat. No. 3,569,938. Eden, et al teach that in a demand paging or request system, caching data in a cache-type high-speed front store (buffer) can make a peripheral storage system appear to have a large capacity, yet provide rapid access to data; rapid access being faster than that provided to the normal backing store. Eden, et al also teach that the backing store can be a retentive store, such as magnetic tape recorders and magnetic disk recorders while the front store can be a volatile store such as a magnetic core store. With the advances in data storage technology, the front store typically includes semiconductive type data storage elements. U.S. Pat. No. 3,839,704 shows another form of the storage hierarchy. An important aspect of storage hierarchies is data integrity. That is, the data received from a user, such as a central processing unit (CPU) or other data handling device, should be returned to the supplying unit either correct or with an indication that errors may exist. It is typical practice in storage hierarchies to move data from a higher level to a lower level for such retentive storage as well as limiting the data in the higher levels such that other data can be stored for rapid access. U.S. Pat. No. 4,020,466 shows copying changes from a highlevel store to a backing store, while U.S. Pat. No. 4,077,059 shows forcing copyback under predetermined conditions. Such copyback operations can consume storage hierarchy performance time, i.e., so much data may be copied back that access to the data by a using unit may be degraded. This problem is partially solved by U.S. Pat. No. 3,588,839 which teaches that the only data that need be copied back from a high-level storage unit to a low-level storage is that data that is altered, i.e., where there is noncongruence between data in a backing store and data in a front store.
Storage hierarchies have taken diverse forms. For example, in accordance with the Eden, et al U.S. Pat. No. 3,569,938 a single high-speed store serviced several users. U.S. Pat. No. 3,735,360 shows that each processor can have its own high-speed store or cache for different performance reasons. Performance of the storage hierarchies also is affected by the algorithms and other controls used to place predetermined data into the cache or high-speed storage portion. Accordingly, U.S. Pat. No. 3,898,624 shows that varying the time of fetching data from a backing store to a front or caching store can be selected by computer operator in accordance with the programs being executed in a using CPU. In this manner, it is hoped that the data resident in the cache or upper level of the hierarchy will be that data needed by the CPU while excess data not needed is not resident. This arrangement allows more useful data to be stored in the higher level storage portion. All of these operations become quite intricate. Accordingly, evaluation programs for storage hierarchies have been used to evaluate how best to manage a storage hierarchy. U.S. Pat. Nos. 3,964,028 and 4,068,304 show performance monitoring of storage hierarchies for achieving these goals. Even at that, much remains to be done in various types of storage hierarchies for enhancing optimum performance while ensuring data integrity. Much of the work with respect to storage hierarchies has occurred in the cache and main memory combinations connected to a using CPU. The principles and teachings from a cached main memory relate directly to caching and buffering peripheral systems, as originally suggested by Eden et al, supra. Of course, main memory has been used prior to Eden, et al for buffering or caching data from a magnetic tape and disk unit for a CPU, i.e., a main memory was not only used as a CPU working store but also as a buffer for peripheral devices.
The performance monitoring referred to above has indicated that it is not always in the best interest of total data processing performance and integrity to always use a caching buffer interposed between a using unit and a backing store. For example, U.S. Pat. No. 4,075,686 teaches that a cache can be turned on and off by special instructions for bypassing the cache. Further, the backing store or memory was segmented into various devices with some of the devices or segments being bypassed, such as for serial or sequential input/output operations. This patent further teaches that for certain commands, it is more desirable to not use cache than to use cache. U.S. Pat. No. 4,268,907 further teaches that for a command specifying the fetching of data words, an indicator flag is set to a predetermined state. Such flag conditions replacement circuits to respond to subsequent predetermined commands to bypass cache storage for subsequently fetched data words when the indicator flag is in the predetermined state to prevent replacement of extensive numbers of data instructions already stored in cache during the execution of such instructions. Further U.S. Pat. No. 4,189,770 shows bypassing cache for operands but using cache for storing instructions.
Disk storage apparatus, also referred to as direct access storage devices (DASD), provide large quantities of random access nonvolatile storage for data processing. Caching the DASD, as suggested above, provides a storage hierarchy with the performance and throughput capability better than that of DASD; it also reduces the cost of data storage, power requirements, and increasing volumetric storage efficiency. Such performance improvement is obtained principally by maximizing the number of data storage accesses which can be satisfied by accessing a copy of the data in the cache rather than by directly accessing the DASD. Management of the storage hierarchy includes dynamically entering data into and deleting data from the cache with the intent of increasing the proportion of the number of accesses that can be satisfied through the cache. Some commands to DASD require access to the device irrespective of whether or not a cache is present. Such commands include read IPL, write home address, write RO and write COUNT KEY DATA. On DASDs manufactured by International Business Machines Corporation, Armonk, N.Y., on such device related commands, the user accesses the DASD, obtains synchronization with the disk rotation (called orientation) and then operates directly with the DASD. When caching is used, some commands such as SEARCH, and so forth, that normally require rotational orientation of the DASD record surfaces with respect to the request can be handled by searching the cache and proceeding as if the cache were the DASD, thereby enhancing performance. It should be noted that hosts have been programmed to optimize accesses to DASD by constructing programs that accommodate DASD head seeks and latency characteristics. The present invention takes advantage of this fact each time a cache miss occurs. Otherwise, the time required to locate allocation space in cache, particularly where a large multi-megabyte cache is employed, requires sufficient time that in high performance DASDs, orientation may be lost during the search. Therefore, rather than enhancing performance, performance of the DASD can actually degrade through the addition of a cache. The present invention ensures total performance enhancement. For multitrack commands, the chain of commands is sensitive to the current relative position of the read/write mechanism with respect to the records. Since the command must be processed against a so-called home address, record zero or record one of an adjacently addressed or next track where orientation sensitivities occur, a penalty in time lost occurs when orientation is lost and is needed. This loss of time is equal to the latency period of the DASD. Therefore, in a multitrack operation two rotations of the DASD disk could be required under certain operating conditions when cache directories are searched for data images or replications stored in cache.
A so-called SEEK HEAD, i.e., a command which causes electronic switching between transducers in a multidisk DASD, is also sensitive to the current position of the read/write mechanism with respect to the rotation disks. Present input/output command chains and the data being accessed on the DASD have been structured in a way that depends upon rotational orientation with the next accessed track in the amount of time no greater than some fixed values, that is there is rotational offset of the data on the disks which allows electronic track switching without loss of rotational orientation. This fixed value of elapsed time has been determined from known device characteristics and is usually close to the time required by noncached DASD to perform the switching operation. Because of the operational characteristics of the peripheral system in a multitrack operation, such loss of time can be magnified because of other operations being performed requiring repeated attempted accesses in a multitrack operation. Accordingly, it is desired to provide a cached DASD which operates in a manner for preventing exposures to loss of orientation while maintaining high data integrity.